Journal Title：Iet Computers And Digital Techniques

IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test.

The key subject areas of interest are:

Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation.

Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance.

Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues.

Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware.

Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting.

Case Studies: emerging applications, applications in industrial designs, and design frameworks.

IET 計(jì)算機(jī)與數(shù)字技術(shù)發(fā)表技術(shù)論文，介紹數(shù)字片上系統(tǒng)設(shè)計(jì)和電子及嵌入式系統(tǒng)測(cè)試各個(gè)方面的最新研究和開發(fā)工作，包括設(shè)計(jì)自動(dòng)化工具（方法、算法和架構(gòu)）的開發(fā)。特別歡迎基于與 CMOS 技術(shù)縮小相關(guān)的問題的論文。它面向計(jì)算機(jī)和數(shù)字系統(tǒng)設(shè)計(jì)和測(cè)試領(lǐng)域的研究人員、工程師和教育工作者。

感興趣的關(guān)鍵主題領(lǐng)域是：

設(shè)計(jì)方法和工具：CAD/EDA 工具、硬件描述語(yǔ)言、高級(jí)和架構(gòu)綜合、硬件/軟件協(xié)同設(shè)計(jì)、基于平臺(tái)的設(shè)計(jì)、3D 堆疊和電路設(shè)計(jì)、片上系統(tǒng)架構(gòu)和 IP 核、嵌入式系統(tǒng)、邏輯綜合、低功耗設(shè)計(jì)和功率優(yōu)化。

仿真、測(cè)試和驗(yàn)證：電氣和時(shí)序仿真、基于仿真的驗(yàn)證、硬件/軟件協(xié)同仿真和驗(yàn)證、混合域技術(shù)建模和仿真、硅后驗(yàn)證、功率分析和估算、互連建模和信號(hào)完整性分析、硬件信任和安全性、可測(cè)試性設(shè)計(jì)、嵌入式核心測(cè)試、片上系統(tǒng)測(cè)試、在線測(cè)試、自動(dòng)測(cè)試生成和延遲測(cè)試、低功耗測(cè)試、可靠性、故障建模和容錯(cuò)。

處理器和系統(tǒng)架構(gòu)：多核系統(tǒng)、通用和專用處理器、DSP 應(yīng)用的計(jì)算算法、算術(shù)和邏輯單元、高速緩存、內(nèi)存管理、協(xié)處理器和加速器、片上系統(tǒng)和網(wǎng)絡(luò)、嵌入式內(nèi)核、平臺(tái)、多處理器、分布式系統(tǒng)、通信協(xié)議和低功耗問題。

可配置計(jì)算：嵌入式內(nèi)核、FPGA、快速原型設(shè)計(jì)、自適應(yīng)計(jì)算、可演化和靜態(tài)和動(dòng)態(tài)可重構(gòu)及可重新編程系統(tǒng)、可重構(gòu)硬件。

針對(duì)可變性、功耗和老化的設(shè)計(jì)：針對(duì)可變性、功耗和老化感知設(shè)計(jì)、內(nèi)存、FPGA、IP 組件、3D 堆疊、能量收集的設(shè)計(jì)方法。

案例研究：新興應(yīng)用、工業(yè)設(shè)計(jì)中的應(yīng)用以及設(shè)計(jì)框架。

Iet Computers And Digital Techniques創(chuàng)刊于2007年，由Wiley出版商出版，收稿方向涵蓋工程技術(shù) - 計(jì)算機(jī)：理論方法全領(lǐng)域，此期刊水平偏中等偏靠后，在所屬細(xì)分領(lǐng)域中專業(yè)影響力一般，過審相對(duì)較易，如果您文章質(zhì)量佳，選擇此期刊，發(fā)表機(jī)率較高。平均審稿速度 12周，或約稿 ，影響因子指數(shù)1.1，該期刊近期沒有被列入國(guó)際期刊預(yù)警名單，廣大學(xué)者值得一試。